1. Field of the Invention
This invention relates in general to an output buffer circuit which is utilized in semiconductor devices such as memory devices.
2. Description of the Prior Art
Prior art output buffer circuits are such as illustrated in FIG. 3 wherein a driver 32 is connected to an output terminal of a sense amplifier 31 that receives at its input the output of memory cells in which information signals are stored and whereby readout signals corresponding to the address signals are sensed. The driver 32 is connected to an input terminal 33 of an output buffer circuit. The output buffer circuit comprises a PMOS transistor 34 and a NMOS transistor 35. The input terminal 33 is connected to the gates of both of the PMOS transistor 34 and the NMOS transistor 35. The source of the PMOS transistor 34 is connected to a suitable power supply voltage and the source of the NMOS transistor 35 is connected to a ground voltage. The drains of the transistors 34 and 35 are connected together and to an output terminal 36.
In the prior art, since each MOS transistors 34 and 35 has the function to serve as an electrostatic protective circuit, it is not necessary to provide a special protective circuit. FIG. 2 illustrates a MOS transistor which has a depletion layer 23 formed in a PN junction 22 formed in an impurity region 21 on the drain D during reverse bias and the MOS transistor itself serves as a protective diode such that breakdown is caused at lower voltage than the electrostatic breakdown voltage on an adjacent part to the surface on the channel side of the PN junction 22 and electrostatic breakdown will be avoided.
However, due to the miniaturization of memory devices, the channel width W of the MOS transistor in the output buffer circuit will become narrower and narrower. As shown in FIG. 4 by the dotted line when the channel width W becomes narrower, the breakdown voltage increases so that it is not possible to protect the output buffer circuit effectively from electrostatic breakdown.
Thus, when the channel width W becomes narrower, the volume of the substrate 24 that encloses the PN junction 22 or the well region 25 becomes relatively larger and as a result, the voltage applied to the depletion layer 23 will be reduced due to the resistance change. Thus, at a particular voltage insulation breakdown occurs instead. Also, the narrow channel width W causes more current to be supplied per unit area which causes electrostatic breakdown to occur at lower voltages.
The breakdown voltage does not increase if the channel width W does not become narrower.
However, unless the channel width W becomes narrower, the ability of the output buffer to drive becomes larger than is desired. If excess current flows when the load capacity 37 is driven, as shown in FIG. 3, harmful influences occur to the power supply voltage or to the ground voltage due to parasitic inductances which may occur and which may cause malfunctions of the circuit.
If on the other hand, the channel length L of the MOS transistor of the output buffer circuit is set to be longer than that of the MOS transistor such as in the memory cells, the channel width W need not be narrowed and the driving ability of the output buffer can be maintained within the desired range.
In such a case, however, the gate capacity which depends on the area of the gate electrode G illustrated in FIG. 2 of MOS transistors 34 and 35 of the output buffer circuit increases as illustrated in solid line in FIG. 4. This may cause undesirable effects such as delay in the operating speed, increased power consumption or undesirable pattern area effects and may result in the necessity to improve the driving ability of the driver 32 in the sense amplifier 32.